A parallel iterative scheduler for asynchronous Optical Packet Switching networks

The work described in this paper was carried out with the support of the BONE project (“Building the Future Optical Network in Europe”); a Network of Excellence funded by the European Commission through the 7th ICT-Framework Program. This research has been partially supported by the project CALM TEC2010-21405-C02-02 (subprogram TCM) funded by the Spanish Ministerio de Innovación y Ciencia and and it is also developed in the framework of "Programa de Ayudas a Grupos de Excelencia de la R. de Murcia, F. Séneca". Pablo Pavon Marino, Maria Victoria Bueno Delgado are with Technical University of Cartagena, Plaza Hospital 1, 30202, Cartagena, Spain (phone: +34 968325952; fax: +34 968325973; e-mail: {pablo.pavon, mvictoria.bueno}@upct. Walter Cerroni, Aldo Campi, Franco Callegati are with the University of Bologna, DEIS Department, Via Venezia 52, 47521 Cesena (FC), Italy (phone: +39 0547 339209; fax: +39 0547 339208; e-mail: {walter.cerroni, aldo.campi, franco.callegati}@unibo.it). Abstract—This paper presents PI-OPS (Parallel-Iterative Optical Packet Scheduler) a parallel-iterative scheduler for asynchronous Optical Packet Switching nodes with optical buffering. Optical packets are assembled by aggregating IP packets, and attaching an optical packet header. Conventional schemes process optical packet headers one by one, in a sequential form. Then, worst case algorithm response time is tightly coupled to switch size. In contrast, in PI-OPS all the optical packets received during a given time window are jointly processed to optimize the delay and output wavelength allocation, applying void filling techniques. The scheduler has a deterministic response time, independent of the traffic arrivals pattern. In addition, PI-OPS has been specifically designed to allow a parallel electronic implementation similar to the ones found in VOQ schedulers. In this respect, we evaluate the traffic loss performance of the scheduler in different settings, to dimension a set of hardware related parameters. Finally, we conduct an emulation of an FPGA implementation of a large-scale version of the scheduler. Results support the feasibility of its implementation.